As complementary metal-oxide-semiconductor (CMOS) technology progresses into the deep sub-micron scale, advanced processes use techniques such as thinner gate oxide, shorter channel length, shallower junction depth, LDD (Lightly-Doped Drain) structure, and/or salicide (Self-Aligned Silicide) diffusion. The use of these processes on the deep sub-micron scale leads to potential degradation of a CMOS IC device due to potential ElectroStatic Discharge (ESD) between high-voltage and low-voltage power supply lines of the CMOS IC device. In order to obtain suitable high resistance to damage from ESD, a CMOS IC device incorporates one or more ESD protection circuits.
A diode in the forward-biased condition can sustain a much higher ESD level than it can in the reverse-biased condition. Thus, a diode string that comprises a plurality of cascaded diodes connected in series is suitable to be used as an ESD protection circuit (e.g., ESD clamp) to clamp the ESD overstress voltage between the high-voltage and low-voltage power lines of the CMOS IC device and protect the device from high voltage stress.